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            IC Compiler 2-CTS培训班
   入.学.要.求

        学员学习本课程应具备下列基础知识:
        ◆ 有数字电路设计和硬件描述语言的基础或自学过相关课程。

   班.级.规.模.及.环.境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:深圳大学成教院/ 电影大厦(地铁一号线大剧院站)【北京分部】:福鑫大楼/北京中山 【武汉分部】:佳源大厦(高新二路) 【南京分部】:金港大厦(和燕路) 【成都分部】:领馆区1号(中和大道)
最近开课时间(连续班/周末班/晚班)
IC Compiler 2-CTS培训班:即将开课,详情请咨询客服。(请抓紧报名)
   实验设备
     ◆课时: 共6天,36学时

        
        ☆合格学员免费颁发相关资格证书,提升您的职业资质
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        可,学员的能力得到大家的认同

        ☆合格学员免费推荐工作
        ★实验设备请点击这儿查看★
   .最.新.优.惠.
       ◆在读学生凭学生证,可优惠500元。
   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

             IC Compiler 2-CTS培训班

 

Overview
????? In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
????? After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.
Objectives
At the end of this workshop the student should be able to:
  • Develop an VMM environment class in SystemVerilog
  • Implement and manage message loggers for printing to terminal or file
  • Build a random stimulus generation factory
  • Build and manage stimulus transaction channels
  • Build and manage stimulus transactors
  • Implement checkers using VMM callback methods
  • Implement functional coverage using VMM callback methods
Audience Profile
????? Design or Verification engineers who develop SystemVerilog testbenches using VMM base classes
Prerequisites
????? To benefit the most from the material presented in this workshop, students should:
Have taken the SystemVerilog Testbench workshop
OR
  • Generating OpenVera testbench templates
  • Creating/Using OpenVera Virtual Ports
  • Developing testbench components as OOP classes
  • Creating Coverage Group for functional coverage
Course Outline
1
  • SystemVerilog class inheritance review
  • VMM Environment
  • Message Service
  • Data model
2
  • Stimulus Generator/Factory
  • Check & Coverage
  • Transactor Implementation
  • Data Flow Control
  • Scenario Generator
  • Recommendations