 PrimeRail培训 |
| 培.养.对.象 |
1.理工科背景，有志于数字集成电路设计工作的学生和转行人员；
2.需要充电，提升技术水平和熟悉设计流程的在职人员；
3.集成电路设计企业的员工内训。
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| 入.学.要.求 |
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学员学习本课程应具备下列基础知识：
◆电路系统的基本概念。 |
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班.级.规.模.及.环.境 |
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为了保证培训效果，增加互动环节，我们坚持小班授课，每期报名人数限5人，多余人员安排到下一期进行。 |
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上课时间和地点 |
上课地点：【上海】：同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】：深圳大学成教院/ 电影大厦(地铁一号线大剧院站)【北京分部】：福鑫大楼/北京中山 【武汉分部】：佳源大厦（高新二路） 【南京分部】：金港大厦(和燕路)
【成都分部】：领馆区1号（中和大道）
最近开课时间(连续班/周末班/晚班）： PrimeRail培训开班时间：即将开课，详情请咨询客服。(请抓紧报名) |
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实验设备 |
◆课时： 共6天,36学时
☆合格学员免费颁发相关资格证书，提升您的职业资质
作为最早专注于嵌入式培训的专业机构，曙海嵌入式提供的证书得到本行业的广泛认
可，学员的能力得到大家的认同。
☆合格学员免费推荐工作
★实验设备请点击这儿查看★ |
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.最.新.优.惠. |
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◆在读学生凭学生证，可优惠500元。 |
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.质.量.保.障. |
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1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
3、培训合格学员可享受免费推荐就业机会。 |
PrimeRail培训 |
第一阶段 |
ObjectivesAt the end of this workshop the student should be able to:
- Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
- Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
- Library Characterization
- Data preparation
- Power Analysis
- PG Parasitic (RC) Extraction
- Dynamic (Transient) Rail Analysis
- Violation Viewing, Reporting and Correction
- What-if Analysis ? Package parasitics and Decap insertion
- Voltage Drop Derated Timing Analysis
- Accurate Hard Macro Modeling
- Power Management( power switch) Cell handling
- Set up PG analysis for hierarchical and top-level
- Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis
Audience Profile
Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the "Block" or "Full-Chip" levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:
- Physical layout
- Physical extraction
- Power simulation
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Static Analysis
- Introduction to Rail Analysis - requirements, capabilities and database preparation
- Power and Timing Model creation
- Power supply, net switching and Transition Time inputs
- Power and Rail Analysis
- Mapping, reporting, querying and what-if Analysis
- Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis
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第二阶段 |
Dynamic ( Transient) Analysis
- Introduction, database requirements and flows
- Library Characterization and LSF
- Cell-Level Dynamic Analysis-PP Run
- Cell-Level Dynamic Analysis-Transient Analysis
- What-if Analysis ? Package Parasitics and Decap Insertion
- Mapping, waveform viewing, reporting and querying
- Tx-Level Dynamic Analysis-Data Preparation
- Tx-Level Dynamic Analysis
- Tx-Level Signal EM Analysis
- Macro Modeling - Memory, Analog, custom or Hardmacro blocks
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