 Virtuoso UltraSim Full-chip Simulator vMMSIM培训 |
| 入.学.要.求 |
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学员学习本课程应具备下列基础知识：
◆ 电路系统的基本概念。 |
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班.级.规.模.及.环.境 |
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为了保证培训效果，增加互动环节，我们坚持小班授课，每期报名人数限5人，多余人员安排到下一期进行。 |
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上课时间和地点 |
上课地点：【上海】：同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】：深圳大学成教院/ 电影大厦(地铁一号线大剧院站)【北京分部】：福鑫大楼/北京中山学院 【武汉分部】：佳源大厦（高新二路） 【南京分部】：金港大厦(和燕路)
【成都分部】：领馆区1号（中和大道）
最近开课时间(连续班/周末班/晚班）：Virtuoso UltraSim Full-chip Simulator vMMSIM培训：2025年5月1日....--即将开课----即将开课，请咨询客服。 |
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学时 |
◆课时： 共6天,36学时
◆外地学员：代理安排食宿（需提前预定）
☆合格学员免费颁发相关资格证书，提升您的职业资质
作为最早专注于嵌入式培训的专业机构，曙海嵌入式学院提供的证书得到本行业的广泛认
可，学员的能力得到大家的认同。
☆合格学员免费推荐工作
★实验设备请点击这儿查看★ |
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.最.新.优.惠. |
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◆团体报名优惠措施：两人95折优惠，三人或三人以上9折优惠 。注意：在读学生凭学生证，即使一个人也优惠500元。 |
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.质.量.保.障. |
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1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持，充分保证培训后出效果；
3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书，提升您的职业资质。专注高端培训13年，曙海提供的证书得到本行业的广泛认可，学员的能力得到大家的认同，受到用人单位的广泛赞誉。 |
Virtuoso UltraSim Full-chip Simulator vMMSIM培训
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Course Description
In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso? UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.
Learning Objectives
After completing this course, you will be able to:
- Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
- Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
- Construct probes and measures for reporting circuit performance during simulation
- Examine postprocessing measurement
- Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
- Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog? HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
- Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
- Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market
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